1. Technical Field
The present application relates, in general, to digital to analog converters.
2. Description of the Related Art
Digital to analog converters (hereafter referred to as “DACs”) attempt to produce a faithful reproduction of an analog continuous-time signal from discrete-time digital samples. In theory, a DAC can be implemented with an array of weighted analog components that are controlled by an incoming digital code. The outputs of the weighted analog components are then summed and filtered to reproduce a continuous-time signal.
One type of DAC is known in the art as an “oversampling” DAC. One example of an oversampling DAC device is shown in FIG. 1.
FIG. 1 shows related-art oversampling DAC device 100. Upsampling and digital interpolation filtering unit 104, composed of 8× upsampling unit 106 and digital interpolation filtering unit 108, receives the digital input signal. In operation, 8× upsampling unit 106 typically samples much faster than the rate at which the digital input signal is expected to change, and tends to create unwanted spectral images. Accordingly, digital interpolation filtering unit 108 receives the output of 8× upsampling unit 106 and removes the unwanted spectral images created by the operation of 8× upsampling unit 106.
Upsampling and digital zero order hold unit 110, composed of 32× upsampling unit 112 and digital zero order hold filtering unit 114 receives the output of digital interpolation filtering unit 108. In particular, 32× upsampling unit 112 receives the output of digital interpolation filtering unit 108. Digital zero order hold filtering unit 114 receives the output of 32× upsampling unit 112, and typically repeats an incoming sample for a number of times equal to the amount of upsampling (e.g., repeating 32 times).
The output of digital zero order hold filtering unit 114 feeds to digital noise shaping loop 119. Digital noise shaping loop 119 contains embedded quantizer unit 117 which typically reduces the number of elements required to perform the actual digital to analog conversion (e.g., such as those illustrated in DAC 118). Digital noise shaping loop 119 typically functions to push much of the digital quantization noise introduced by the quantization operation out of the signal band of interest and provides a high pass noise transfer function. The input to digital noise shaping loop 119 typically sees unity gain to the output of digital noise shaping loop 119, so signals of interest are generally not degraded by the operation of digital noise shaping loop 119.
The output of digital noise shaping loop 119 controls the switching of the actual DAC elements of DAC 118. In some cases, the designer may also choose to add element linearization circuitry which is controlled by the output of the digital noise shaping loop 119 and in turn dictates the switching of the actual DAC elements of DAC 118, such that the resulting output of the DAC array is unaffected by mismatches between the DAC elements. The actual DAC elements of DAC 118 typically deliver either charge or current to a summing node in order to produce a reconstructed analog signal.
The output of DAC 118 is received by analog postfilter 120. Generally, analog postfilter 120 is configured to reduce the out-of-band noise resulting from shaped quantization performed by digital noise shaper 116. Those having ordinary skill in the art will appreciate that, for a fully monolithic integrated circuit application, it is desirable that analog postfilter 120 be of at least the order of digital noise shaping loop 119 in order to attenuate out-of-band noise. Having analog postfilter 120 be at least the same order as noise shaping loop 119 helps prevent interference of out of band noise with other circuit blocks on a monolithic chip, and also avoids undesirable mixing with other out-of-band signals.
In modern integrated circuit (e.g., CMOS) processes, the digital circuitry used in upsampling, noise shaping, and analog postfiltering of the actual DAC element switching can be scaled down to the point where power and area consumption are very low for a given noise specification. However, the analog performance of such scaled down systems is often limited by inherent component noise, which has generally not been reduced as integrated circuit (e.g., CMOS) process resolution has increased. In response to this dilemma, related-art circuit techniques have been developed to reduce noise and power consumption. However, notwithstanding these related art techniques, a more or less constant need exists in the art for D/A techniques which reduce noise and power consumption, especially in scaled down monolithic integrated circuit applications.
In addition to the foregoing, there are additional problems associated with D/A converters having differing input (digital) and output (analog) common mode references. This problem originates from the fact that system designers typically assume that their negative references for both digital and analog components are the same—namely 0V. System designers do this because 0V is a convenient reference and it provides them with the maximum signal swing for a given positive reference. Analog reference voltages should typically be from rail-to-rail, that is from 0V to the maximum supply voltage, because the analog output swing must be as wide as possible. However, system designers have recognized that the negative digital reference does not necessarily need to be at 0V. The negative digital reference may be set higher so as to make the digital common mode the same as the analog common mode. In this case, system designers have recognized that the common mode references for the digital and analog need not be split, and in fact, for DCT (described following), the common mode references may be set to a value independent of the actual digital/analog common mode.
The drawback to this approach in D/A converter designs such as where a DCT postfilter is integrated with a D/A converter, however, is that by decreasing the difference between the positive and negative reference voltages, the amplitude of the signal that comes into the analog postfilter is also decreased. Since the noise of the analog postfilter is the same as before, the signal-to-noise ratio is now in turn decreased. In order to restore the signal-to-noise ratio, the power and area of the analog postfilter must increase to reduce the noise. Thus, the split-common mode reference scheme is preferred because the amplitude of the signal incoming to the analog postfilter need not be decreased. However, the split common mode reference scheme does cause problems as outlined above. Accordingly, a need exists for a scheme that will utilize a split common mode reference, while alleviating some of the problems associated with the scheme.